To construct 3D devices, high precision metal interconnects and insulating overlayers are introduced sequentially, building the device from the bottom up. However, the conditions for insulator deposition are harsh, and can destroy or block the nm-width metal features. Our research at the nanometer level will focus on producing materials that bind specifically to the metal interconnects, protecting them during exposure to the demanding conditions used in dielectric (insulator) deposition.

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If you are interested in learning more about our current projects at the Micro level please contact our Managing Director, Jyoti Kotecha, or email a member of the research team.