Modern technology uses metals for information transfer and data processing. Mobile phones, computers and communications infrastructure use devices manufactured with metal interconnects, drawn with micro or nanometer precision. As the size of these devices decreases, so must their microprocessors, creating significant challenges in the production of miniaturized metal patterns. Area selective atomic layer deposition (AS-ALD) is a promising technique being explored to enable the production of such patterns with atomic-level precision, in a three-dimensional manner, essential in modern device construction.  

 

To construct 3D devices, high precision metal interconnects and insulating overlayers are introduced sequentially, building the device from the bottom up. However, the conditions for insulator deposition are harsh, and can destroy or block the nm-width metal features. Our research at the nanometer level will focus on producing materials that bind specifically to the metal interconnects, protecting them during exposure to the demanding conditions used in dielectric (insulator) deposition.

 

If you are interested in learning more about our current projects at the macro level please contact our Managing Director, Jyoti Kotecha.